Prior art EEPROM devices place an erase window in the vicinity of an active or channel region of a memory cell transistor. This erase window typically represents a "tunnel" oxide or "leaky" insulating layer. An EEPROM may be quickly programmed or deprogrammed by applying a sufficiently high voltage potential across the erase window so that hot electrons tunnel through the erase window.
EEPROM devices may be programmed or deprogrammed slowly by placing a relatively low voltage potential across the erase window. Accordingly, the placement of an erase window in the active region of a memory cell transistor presents a reliability problem because normal operating conditions encountered while reading the EEPROM place a relatively low voltage potential across the erase window. Consequently, over long periods of time, the normal operation of the EEPROM device may alter a program stored in the EEPROM device.
One prior art solution to this problem is shown in U.S. Pat. No. 4,561,004 by Chang-Kaing Kuo and Shyh-Chang Tsaur, assigned to the assignee of the present invention. This solution places an erase window away from the active region of a memory cell transistor. Thus, a program stored in an EEPROM device remains unaltered in spite of extensive normal read operations because the read operations do not place a voltage potential across the erase window. However, this solution dedicates large sections on the semiconductor substrate to this erase window function. An undesirably low density EEPROM results. Consequently, the industry has a need for an EEPROM structure which removes erase windows from the active regions of memory cell transistors without dedicating semiconductor substrate area to that function.